DocumentCode
1831756
Title
An experimental study on multi-island structures for single-electron tunneling based threshold logic
Author
Puthucode, Venketeshwaran ; Chen, Chunhong
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON
fYear
2008
fDate
18-21 May 2008
Firstpage
600
Lastpage
603
Abstract
In this paper we investigate two different multi-island structures (namely mesh-structure and clique-structure) based on Single-Electron Tunneling (SET) technology, and study the experimental behaviors in terms of their tolerance to random background charges (RBCs) which are a big concern with SET logic. As an alternative redundancy scheme, both structures are applied to an SET-based NAND logic gate for detailed discussions. Our main objective is to show that the proposed multi-island structures are more tolerant to RBCs over the islands when compared with single-island SET logic. Further comparison between the two structures is also shown through the experiments.
Keywords
CMOS logic circuits; logic gates; single electron devices; tunnelling; NAND logic gate; clique-structure; mesh-structure; multiisland structures; random background charges; single-electron tunneling technology; Circuits; Electrodes; Electrons; Logic devices; Logic gates; Redundancy; Switches; Threshold voltage; Tunneling; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location
Seattle, WA
Print_ISBN
978-1-4244-1683-7
Electronic_ISBN
978-1-4244-1684-4
Type
conf
DOI
10.1109/ISCAS.2008.4541489
Filename
4541489
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