A 1.5-V 4-GHz dynamic-loading regenerative frequency doubler in a 0.35-/spl mu/m CMOS process

Author

Wong, J.M.C. ; Luong, H.C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

1

fYear

2002

fDate

2-7 June 2002

Firstpage

573

Abstract

This paper proposes a new topology of a frequency doubler using a dynamic-loading technique to achieve higher operating frequency, larger output swing, larger bandwidth and lower phase noise compared to traditional designs. Implemented in a standard 0.35-/spl mu/m digital CMOS process and at a 1.5-V supply, the proposed frequency doubler measures a maximum operating output frequency of 4 GHz with a bandwidth of 2.4 GHz while consuming a power of 3.7mW. The single-ended output amplitude is ranging from -3.0 to -6.5 dBm, and the phase noise is as low as -111dBc/Hz @ 500kHz offset.

Keywords

CMOS analogue integrated circuits; frequency multipliers; integrated circuit noise; phase noise; 0.35 micron; 1.5 V; 2.4 GHz; 3.7 mW; 4 GHz; CMOS process; bandwidth; dynamic loading; output swing; phase noise; regenerative frequency doubler; Bandwidth; CMOS process; CMOS technology; Circuits; Clocks; Design engineering; Differential amplifiers; Frequency synthesizers; Phase noise; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2002 IEEE MTT-S International

Conference_Location

Seattle, WA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7239-5

Type

conf

DOI

10.1109/MWSYM.2002.1011685

Filename

1011685