Title :
A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology
Author :
Lien, Yuan-Ching ; Lee, Jri
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS technology; analog-digital converters; digital correction; offset calibration; power 30 mW; size 90 nm; word length 6 bit; Bandwidth; CMOS technology; Calibration; Circuits; Error correction; Preamplifiers; Routing; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708725
