A serial communication infrastructure for multi-chip address event systems

In recent years there have been an increasing number of research groups that have begun to develop multi-chip address-event systems. The communication protocol used to transmit signals between these systems´ components is based on the address-event representation (AER). It is therefore important to have access to robust and reliable AER communication infrastructures for streamlining the systems´ development and prototyping stages. We propose an AER communication infrastructure that can be easily interfaced to workstations or laptops during a prototyping phase, and that can be embedded into compact and low-cost systems in the application phase. The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125 MHz for 32 bit AEs.