• DocumentCode
    1832071
  • Title

    A CMOS high IIP2 mixer for multi-standard receivers

  • Author

    Vahidfar, M.B. ; Shoaei, O.

  • Author_Institution
    Dipt. di Elettron., Univ. degli Studi di Pavia, Pavia
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    656
  • Lastpage
    659
  • Abstract
    An IIP2 enhancement technique for CMOS down converter mixers is introduced in this paper. The technique is based on canceling second order intermodulation components generated in input pseudo differential transconductor, by injecting a nonlinear current to the mixer. This current is controlled by a feedback loop which provides enough bandwidth for high channel bandwidth applications like UMTS as well as GSM, therefore this cancellation technique can be employed in multi-standard mixers. A CMOS mixer demonstrating the performance for UMTS standard is designed in a 65 nm technology. The simulation results show that the differential and common mode IIP2 of the mixer are improved about 15 dB and 27 dB respectively, while cancellation circuit consumes less than 2 mA.
  • Keywords
    CMOS integrated circuits; convertors; mixers (circuits); CMOS down converter mixer; IIP2 enhancement technique; high channel bandwidth application; intermodulation component; multistandard mixer; nonlinear current; pseudodifferential transconductor; second-order input intercept point; 1f noise; 3G mobile communication; Bandwidth; CMOS technology; Cellular phones; Circuits; Feedback loop; Frequency; GSM; Transconductors; CMOS; IIP2; Mixer; Multi-standard; second order intermodulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541503
  • Filename
    4541503