Title :
A 4.25GHz–4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement
Author :
Nandwana, Romesh Kumar ; Anand, Tejasvi ; Saxena, Shanky ; Seong-Joong Kim ; Talegaonkar, Mrunmay ; Elkholy, Ahmed ; Woo-Seok Choi ; Elshazly, Amr ; Hanumolu, Pavan Kumar
Author_Institution :
Univ. of Illinois, Urbana, IL, USA
Abstract :
A calibration-free ring oscillator based fractional-N clock multiplier using hybrid phase/current-mode phase interpolator is presented. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25GHz-to-4.75GHz with in-band noise floor of -104dBc/Hz and 1.5ps integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8dB.
Keywords :
CMOS integrated circuits; MMIC frequency convertors; MMIC oscillators; clocks; current-mode circuits; field effect MMIC; frequency multipliers; phase locked loops; phase noise; CMOS process; FoM; calibration-free fractional-N ring PLL; calibration-free ring oscillator based fractional-N clock multiplier; frequency 4.25 GHz to 4.75 GHz; hybrid phase-current-mode phase interpolator; in-band noise floor; phase noise improvement; size 65 nm; time 1.5 ps; Clocks; Detectors; Jitter; Phase locked loops; Phase noise; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858446
