Title :
A 320-MHz 8bit × 8bit pipelined multiplier in ultra-low supply voltage
Author :
Liang, Yung-Chih ; Huang, Ching-Ji ; Yang, Wei-Bin
Author_Institution :
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu
Abstract :
This paper presents a 0.5-V ultra-low voltage multiplier. In order to achieve ultra-low voltage and high speed operation, we modify the traditional pipelined architecture and adopt a PMOS forward body bias control technique, a symmetric signal path full-adder structure and a synchronous output D flip flop. Fabricated in 130 nm CMOS technology, the measured operation rate of 8bit times 8bit pipelined multiplier get up to 320-MHz clock rate and the power consumption is about 1.48 mW from 0.5-V power supply.
Keywords :
CMOS integrated circuits; UHF integrated circuits; adders; flip-flops; low-power electronics; voltage multipliers; CMOS fabrication technology; PMOS forward body bias control technique; clock rate; frequency 320 MHz; modified traditional pipelined architecture; pipelined multiplier high speed operation; power 1.48 mW; power consumption; size 130 nm; symmetric signal path full-adder structure; synchronous output D flip flop; ultra-low supply voltage; ultra-low voltage multiplier; voltage 0.5 V; Capacitance; Circuit synthesis; Contacts; Costs; Delay effects; Electricity supply industry; MOS devices; Propagation delay; Solid state circuits; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708732
