Design of energy efficient 10ps per bit adder circuits in CMOS

Author

Navarro-Botello, Victor ; Montiel-Nelson, Juan A. ; Nooshabadi, Saeid

Author_Institution

Inst. for Appl. Microelectron., Univ. of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

85

Lastpage

88

Abstract

This work presents the experimental results, from chip measurements, of ripple carry adder circuits using a new CMOS logic family-feedthrough logic (FTL). A 14-bit low power FTL adder performs faster, (2.6 times smaller propagation time delay, and 1.85 times higher maximum frequency), and provides a better energy efficiency (67.9% saving), when compared with the dynamic domino CMOS logic style. The 18-bit high speed FTL, working at its maximum frequency, outperforms the dynamic domino logic in terms of the propagation delay (19.5 times less), maximum frequency (12.1 times more), and energy efficiency per bit (96.7% better).

Keywords

CMOS logic circuits; adders; high-speed integrated circuits; integrated circuit design; logic design; CMOS logic family-feedthrough logic; FTL adder; chip measurements; dynamic domino logic performance; energy efficiency; propagation delay; ripple carry adder circuits; time 10 ps; Adders; Arithmetic; CMOS logic circuits; Clocks; Energy efficiency; Frequency; Logic design; MOS devices; Propagation delay; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708735

Filename

4708735