A novel decimal-to-decimal logarithmic converter

This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal logarithmic converter. Two approaches, binary-based decimal approximation algorithm (algorithm 1) and decimal linear approximation algorithm (algorithm 2), are proposed and investigated. It shows that decimal linear approximation algorithm (algorithm 2) is error-free in conversion between decimal and binary formats and also able to reduce maximum absolute error from binary-based algorithm 1´s 0.00399 (integer cases) and 0.0483 (fraction cases) to 0.000994 (both cases). The Algorithm 2 is modeled in VHDL and implemented using combinational logic only in a Xilinx Virtex-II Pro P30 FPGA device. The logarithms results can be obtained in a single clock cycle, running at 50.9 MHz.