Title :
Low-power logarithmic number system addition/subtraction and their impact on digital filters
Author :
Kouretas, I. ; Basetas, Ch ; Paliouras, V.
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Patras, Patras
Abstract :
This paper discusses techniques for low-power addition/subtraction in the logarithmic number system (LNS) and evaluates their impact on digital filter implementation. Initially, the impact of partitioning the look-up tables (LUT) required for addition/subtraction on complexity, performance, and power dissipation is studied. Subsequently techniques for the low-power implementation of an LNS multiply- accumulate (MAC) unit are investigated. The obtained LNS MACs are used for the design of digital filters. Synthesis of LNS-based digital filters using a 0.18 mum 1.8 V CMOS standard-cell library, reveal that significant power dissipation savings are possible at no performance penalty, when compared to linear two´s-complement equivalent.
Keywords :
CMOS digital integrated circuits; computational complexity; digital filters; integrated circuit design; CMOS standard-cell library; digital filter implementation; digital filters; logarithmic number system; look-up tables; low power addition-subtraction; multiply- accumulate unit; power dissipation; size 0.18 mum; voltage 1.8 V; Complexity theory; Digital filters; Floating-point arithmetic; Power dissipation; Signal processing; Signal synthesis; Software libraries; Switching circuits; Table lookup; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541512
