• DocumentCode
    1832267
  • Title

    Force directed Mongrel with physical net constraints

  • Author

    Hur, Sung-Woo ; Cao, Tung ; Rajagopal, Karthik ; Parasuram, Yegna ; Chowdhary, Amit ; Tiourin, Vladimir ; Halpin, Bill

  • Author_Institution
    Donga Univ., Pusan, South Korea
  • fYear
    2003
  • fDate
    2-6 June 2003
  • Firstpage
    214
  • Lastpage
    219
  • Abstract
    This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, force-directed according to H. Eisenmann and F.M. Johannes (1998) and T. Cao et al. (2003) and Mongrel by S. Hur and J. Lillis (2000). It combines the strengths of force directed global placement with Mongrel´s cell congestion removal to significantly improve the quality of placement during the difficult overlap removal stage of global placement. This is accomplished by using the spreading force in according to H. Eisenmann and F. M. Johannes (1998) to direct and control Mongrel´s ripple move optimization. This new placer is called force directed Mongrel (FD-Mongrel). FD-Mongrel also incorporates physical net constraints according to T. Cao et al. (2003), and improves the congestion model for sparse placements. We propose a new placement flow that uses a limited number of the spreading iterations of generic global placement by H. Eisenmann and F. M. Johannes (1998) to form a preliminary global placement. We then use the new FD-Mongrel described in this paper to remove cell overlaps, while meeting net constraints and optimizing wirelength. We present results on wirelength as well as timing driven placement flows.
  • Keywords
    circuit optimisation; integrated circuit interconnections; integrated circuit modelling; very high speed integrated circuits; FD-Mongrel; Mongrel cell congestion removal; force directed Mongrel; global placement algorithm; limited spreading iterations; optimizing wirelength; overlap removal stage; physical net constraints; sparse placements; timing driven placement flows; Algorithm design and analysis; Circuits; Constraint optimization; Delay; Design optimization; Force control; Permission; Semiconductor process modeling; Timing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2003. Proceedings
  • Print_ISBN
    1-58113-688-9
  • Type

    conf

  • DOI
    10.1109/DAC.2003.1218966
  • Filename
    1218966