Title :
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique
Author :
Chin-Yu Lin ; Tai-Cheng Lee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1st and the 2nd stages and active residue amplification between the 2nd and the 3rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate.
Keywords :
analogue-digital conversion; low-power electronics; SNDR; analog-to-digital converter; frequency 5 MHz; near Nyquist-rate; passive residue transfer technique; pipelined successive approximation architecture; pipelined-SAR ADC; power 5.3 mW; voltage 1 V; word length 12 bit; Arrays; CMOS integrated circuits; CMOS technology; Calibration; Capacitors; Noise; Very large scale integration;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858452
