DocumentCode :
1832330
Title :
Realizable parasitic reduction using generalized Y-Δ transformation
Author :
Qin, Zhanhai ; Cheng, Chung-Kuan
fYear :
2003
fDate :
2-6 June 2003
Firstpage :
220
Lastpage :
225
Abstract :
We propose a realizable RCLK-in-RCLK-out parasitic reduction technique. The method employs generalized Y-Δ transformation. In our method, admittances are kept in their original rational forms of s, and their orders are reduced by truncating high-order terms. Therefore reduced admittances match the low-order terms in exact admittances. First-order realization of admittances is guaranteed, and higher-order realization is achieved by template optimization using geometric programming. The algorithm uniquely uses common-factor identification and cancellation operations to make Y-Δ transformation numerically stable. The experiment shows that our method can achieve higher reduction ratio than TICER and comparable simulation results with PRIMA.
Keywords :
circuit analysis computing; circuit optimisation; circuit simulation; geometric programming; transfer functions; Y-Delta transformation; common-factor cancellation; common-factor identification; geometric programming; realizable parasitic reduction; template optimization; truncating high-order terms; Admittance; Algorithm design and analysis; Analytical models; Circuit simulation; Data mining; Gaussian processes; Graph theory; Integrated circuit interconnections; Permission; Transfer functions;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
Type :
conf
DOI :
10.1109/DAC.2003.1218968
Filename :
1218968
Link To Document :
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