Title :
A 60GHz variable-gain LNA in 65nm CMOS
Author :
Natarajan, Arun ; Nicolson, Sean ; Tsai, Ming-Da ; Floyd, Brian
Author_Institution :
IBM T.J Watson Res. Center, Yorktown Heights, NY
Abstract :
A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.
Keywords :
CMOS integrated circuits; attenuators; low noise amplifiers; millimetre wave amplifiers; notch filters; LNA; compression point; four-stage low-noise amplifier; frequency 210 GHz; frequency 60 GHz; gain 15 dB; image rejection; noise figure 5.9 dB; power 30.8 mW; reflection-type attenuator; size 65 nm; tunable notch filter; variable attenuator; variable gain; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708743