• DocumentCode
    1832379
  • Title

    P-4 process. A novel high-density, low-cost multilayer planar thin-film PWB technology

  • Author

    Li, Weiping ; Tummala, Rao

  • Author_Institution
    Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    1998
  • fDate
    25-28 May 1998
  • Firstpage
    151
  • Lastpage
    157
  • Abstract
    The advantages of thin film on PWB wiring substrate (MCM-D/L) include sequential fabrication and blind/buried microvias to enable fine-line, high-density wiring; and PWB-compatible materials and processes to ensure low cost. Currently, the majority of sequential build-up activities focuses on one or two layers of thin film wiring for surface redistribution. The trends in IC technology, however, require high-density, multilayer thin film interconnection in the next few years. A novel plated-post, photo-polymer (P-4) technology is described in this study, which offers a solution to multilayer thin-film buildup of planar structures on PWBs. The key to this P-4 process is the unique microvia formation and metallization processes. Copper posts are electroplated prior to photo-polymer dielectric layer coating. Microvias are formed right on top of the posts with a significantly reduced aspect ratio compared to conventional microvias. The conductor lines and via posts are fabricated by semi-additive copper plating to achieve fine feature size and minimize waste. As a result, excellent planarity was achieved, which enables the stacking of vias in consecutive layers. Key material and process issues relevant to the P-4 process are addressed. Variation and possible extension of this technology are also explored
  • Keywords
    integrated circuit interconnections; integrated circuit packaging; multichip modules; wiring; MCM-D/L; P-4 process; PWB-compatible materials; aspect ratio; blind microvias; buried microvias; feature size; high-density wiring; low-cost multilayer technology; metallization processes; microvia formation; multilayer thin film interconnection; photo-polymer dielectric layer coating; planar thin-film PWB technology; plated-post photo-polymer technology; semi-additive plating; sequential fabrication; stacking; Conducting materials; Copper; Costs; Dielectric thin films; Fabrication; Metallization; Nonhomogeneous media; Substrates; Transistors; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components & Technology Conference, 1998. 48th IEEE
  • Conference_Location
    Seattle, WA
  • ISSN
    0569-5503
  • Print_ISBN
    0-7803-4526-6
  • Type

    conf

  • DOI
    10.1109/ECTC.1998.678685
  • Filename
    678685