Title :
A test generation system for path delay faults
Author :
Patil, Srinivas ; Reddy, Sudhakar M.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
A complete test pattern generation system for path delay faults is presented. The test pattern generator is based on PODEM using a 5-valued logic. Techniques to prune the search space for test pattern generation are proposed. Since the number of paths for test generation can be exponential in the number of lines in the network, criteria and efficient algorithms to prune the number of paths for test generation are presented. The test generation system is evaluated using the ISCAS combinational benchmark circuits
Keywords :
combinatorial circuits; delays; fault location; logic testing; many-valued logics; 5-valued logic; ISCAS combinational benchmark circuits; PODEM; path delay faults; search space; test generation system; test pattern generation; Circuit faults; Circuit testing; Clocks; Delay systems; Logic circuits; Logic testing; Propagation delay; Sequential circuits; System testing; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63324
