A 0.35μm CMOS sub-1V low-quiescent-current low-dropout regulator

Author

Hwang, Yuh-Shyan ; Lin, Ming-Shian ; Hwang, Bo-Han ; Chen, Jiann-Jong

Author_Institution

Nat. Taipei Univ. of Technol., Taipei

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

153

Lastpage

156

Abstract

A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.

Keywords

CMOS digital integrated circuits; amplifiers; system-on-chip; voltage regulators; CMOS processes; current 103 nA; current 50 mA; digital error amplifier; low-quiescent current; power supply; size 0.35 mum; sub-lV CMOS low-dropout voltage regulator; voltage 0.5 V; voltage 0.9 V; Batteries; Capacitors; Circuits; Digital audio players; Energy consumption; Inverters; Power dissipation; Power supplies; Regulators; Voltage control; digital error amplifier; low-dropout regulator; low-quiescent current;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708751

Filename

4708751