• DocumentCode
    1833061
  • Title

    Device degradation and resilient computing

  • Author

    Glosekotter, Peter ; Greveler, Ulrich ; Wirth, Gilson I.

  • Author_Institution
    Univ. of Appl. Sci. Miinster, Munster
  • fYear
    2008
  • fDate
    18-21 May 2008
  • Firstpage
    828
  • Lastpage
    831
  • Abstract
    In this paper, we study the impact of recent scaling trends on device degradation effects as well as their impact on microarchitecture. A new binning strategy is proposed that takes into account the individual degradation of the processing nodes. The vitality of each processing node is derived from its duty- cycle. By means of random sampling and statistical analysis, the duty-cycle is captured in a resource and time efficient way so that it is feasible to observe more than 100 processing nodes with a single sampling unit. Applications of this kind of degradation handling can primarily be found where conventional reliability verification and life-test acceleration techniques such as burn-in cannot be used anymore due to their complexity and inherent constraints.
  • Keywords
    integrated circuit testing; life testing; statistical analysis; binning strategy; device degradation; life-test acceleration; random sampling; reliability verification; resilient computing; scaling; statistical analysis; Acceleration; Circuits; Degradation; Hot carriers; MOSFETs; Microarchitecture; Niobium compounds; Sampling methods; Stress; Titanium compounds; NBTI; device degradation; duty-cycle; microarchitecture; on-chip measurement; relaxation; resiliency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4244-1683-7
  • Electronic_ISBN
    978-1-4244-1684-4
  • Type

    conf

  • DOI
    10.1109/ISCAS.2008.4541546
  • Filename
    4541546