• DocumentCode
    1833176
  • Title

    Automatic application-specific instruction-set extensions under microarchitectural constraints

  • Author

    Atasu, Kubilay ; Pozzi, Laura ; Ienne, Paolo

  • Author_Institution
    Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland
  • fYear
    2003
  • fDate
    2-6 June 2003
  • Firstpage
    256
  • Lastpage
    261
  • Abstract
    Many commercial processors now offer the possibility of extending their instruction set for a specific application - that is, to introduce customized functional units. There is a need to develop algorithms that decide automatically, from high-level application code, which operations are to be carried out in the customized extensions. A few algorithms exist but are severely limited in the type of operation clusters they can choose and hence reduce significantly the effectiveness of specialization. In this paper, we introduce a more general algorithm which selects maximal-speedup convex subgraphs of the application dataflow graph under fundamental microarchitectural constraints, and which improves significantly on the state of the art.
  • Keywords
    application specific integrated circuits; data flow graphs; instruction sets; microprocessor chips; system-on-chip; application dataflow graph; application-specific instruction-set; high-level application code; instruction-set extensions; maximal-speedup convex subgraphs; microarchitectural constraints; Algorithm design and analysis; Application specific processors; Clustering algorithms; Design methodology; Instruction sets; Laboratories; Microarchitecture; Permission; Process design; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2003. Proceedings
  • Print_ISBN
    1-58113-688-9
  • Type

    conf

  • DOI
    10.1109/DAC.2003.1219004
  • Filename
    1219004