Design of a high efficiency reconfigurable pipeline processor on next generation portable device

In this paper, we propose a reconfigurable pipeline processor to support 128/256/512/1024/1536/2048-point 1D FFT/IFFT computations and 16×16 2D DCT computation. To adopt the radix-4²+radix-2ⁿ algorithm, the proposed single path delay feedback (SDF) based architecture achieves low computation complexity, low cost and high utilization rate advantages. So as to further reduce the cost of constant multiplier, the complex conjugate symmetry rule and sub-expression elimination algorithm have been used on the shift-and-add circuit without complex multiplier. Moreover, from the derivation results, the proposed architecture meets the high efficiency for next-generation portable device requirements on LTE and HEVC standard.