Title :
A fast GDDR5 read CRC calculation circuit with read DBI operation
Author :
Yoon, Sang-Sic ; Kim, Bo-Kyeom ; Kim, Yong-Ki ; Chung, Byongtae
Author_Institution :
Memory R&D, Hynix Semicond. Inc., Icheon
Abstract :
The GDDR5 provides cyclic redundancy check (CRC) function to ensure a high speed operation. The GDDR5 calculates the CRC with read data and transmits the results on error detection code (EDC) pins. This paper presents a scheme to reduce calculation time of CRC when the read data bus inversion (DBI) is enabled. This scheme is applied to GDDR5 product manufactured in 66 nm CMOS process technology and its bandwidth is measured to be greater than 4.0 Gbps on the electric field test.
Keywords :
cyclic redundancy check codes; error detection codes; CMOS process technology; GDDR5; cyclic redundancy check function; data bus inversion; error detection code pins; size 66 nm; Asynchronous transfer mode; Circuit synthesis; Cyclic redundancy check; Graphics; Pins; Random access memory; Registers; Research and development; Solid state circuit design; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708775
