DocumentCode
1833249
Title
A charge recycling TCAM with Checkerboard Array arrangement for low power applications
Author
Kusumoto, Takahito ; Ogawa, Daisuke ; Dosaka, Katsumi ; Miyama, Masayuki ; Matsuda, Yoshio
Author_Institution
Grad. Sch. of Natural Sci. & Technol., Kanazawa Univ., Kanazawa
fYear
2008
fDate
3-5 Nov. 2008
Firstpage
253
Lastpage
256
Abstract
A low power and low noise Ternary Content Addressable Memory (TCAM) architecture is proposed. A TCAM is a powerful engine for search and sort processing, but it has serious power consumption and power line noise problems. To solve these problems, we have developed a charge recycling scheme for match lines, search lines and a Checkerboard Array arrangement. By using these technologies, TCAM power and power line noise can be reduced by 50 % when compared with conventional designs.
Keywords
MOSFET; integrated memory circuits; low-power electronics; NMOS search transistors; TCAM; charge recycling; checkerboard array arrangement; low power applications; match lines; power consumption; power line noise; search lines; ternary content addressable memory architecture; Associative memory; CADCAM; Computer aided manufacturing; Energy consumption; Impedance; Low voltage; MOS devices; Multilevel systems; Noise reduction; Recycling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location
Fukuoka
Print_ISBN
978-1-4244-2604-1
Electronic_ISBN
978-1-4244-2605-8
Type
conf
DOI
10.1109/ASSCC.2008.4708776
Filename
4708776
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