• DocumentCode
    1833264
  • Title

    Synchronous bus arbitration with constant logic per module

  • Author

    Alnuweiri, Hussein M.

  • Author_Institution
    Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
  • fYear
    1994
  • fDate
    26-29 Apr 1994
  • Firstpage
    35
  • Lastpage
    41
  • Abstract
    A novel technique for distributed synchronous bus arbitration is presented. The proposed scheme is based on two orthogonal arbitration functions, one that employs bounded-weight binary codes, and another that employs unitary codes. This scheme trades off bus-width with arbitration-time and arbitration logic per device, such that both arbitration time and arbitration logic (per device) can be reduce by increasing bus width. Alternatively, this method allows the number of devices connected to a bus to be increased without changing the arbitration logic of each device (or the number of arbitration steps), only the width of the arbitration bus must be increased in this case
  • Keywords
    parallel architectures; protocols; system buses; arbitration logic per device; arbitration-time; bounded-weight binary codes; bus width; bus-width; constant logic per module; distributed synchronous bus arbitration; synchronous bus arbitration; unitary codes; Binary codes; Clocks; Combinational circuits; Delay effects; Encoding; Feedback; Logic devices; Metastasis; Signal processing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1994. Proceedings., Eighth International
  • Conference_Location
    Cancun
  • Print_ISBN
    0-8186-5602-6
  • Type

    conf

  • DOI
    10.1109/IPPS.1994.288321
  • Filename
    288321