Constraint synthesis for environment modeling in functional verification

Modeling design environment with constraints instead of a traditional testbench is advantageous in a hybrid verification framework that encompasses simulation and formal verification. This movement is gaining popularity n industry and sparks research in the constraint-based environment modeling and stimulus generation problem. We present an approach, called constraint synthesis, to this problem. Constraint synthesis falls in the general category of parametric Boolean equation solving but is novel in utilizing don´t care information unique to hardware constraints and heuristic variable removal to simplify the solution. Experimental results have demonstrated the effectiveness of the proposed approach.