1-Gb/s mixed-mode BPSK demodulator using a half-rate linear phase detector for 60-GHz wireless PAN applications

Author

Choi, Kwang-Chun ; Kim, Duho ; Ko, Minsu ; Choi, Woo-Young

Author_Institution

Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul

fYear

2008

fDate

3-5 Nov. 2008

Firstpage

357

Lastpage

360

Abstract

A mixed-mode high-speed binary phase-shift keying (BPSK) demodulator for IEEE802.15.3c mm-wave wireless personal area network (WPAN) application is realized with 0.18 mum CMOS process. The demodulator core consumes 23.4 mW from 1.8 V power supply while the chip area is 165 times 110 PMZ. The power-consumption is less than that of the conventional BPSK demodulators and the chip-size is smaller. The proposed circuit is verified by 1-meter 60-GHz wireless link tests with 1-Gb/s data.

Keywords

CMOS integrated circuits; demodulators; personal area networks; phase shift keying; CMOS process; bit rate 1 Gbit/s; frequency 60 GHz; half-rate linear phase detector; mixed-mode high-speed binary phase-shift keying demodulator; power 23.4 mW; power supply; power-consumption; voltage 1.8 V; wireless link tests; wireless personal area network; Binary phase shift keying; Circuit noise; Demodulation; Detectors; Land mobile radio; Mobile communication; Phase detection; Phase noise; Radiofrequency integrated circuits; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Conference_Location

Fukuoka

Print_ISBN

978-1-4244-2604-1

Electronic_ISBN

978-1-4244-2605-8

Type

conf

DOI

10.1109/ASSCC.2008.4708801

Filename

4708801