A 24GHz low-power CMOS receiver design

A 24 GHz low-power CMOS RF receivers for indoor wireless application is developed in this paper. This paper presents a novel approach to integrate the RF front-end circuits, and realizes the manufacture of SoC (System on a Chip) design. The proposed RF IC includes a low-noise amplifier (LNA), a down-conversion mixer, a voltage-controlled oscillator (VCO) and a variable gain amplifier (VGA). For the demands of a low- power design, the LNA and VCO were designed with current- reused technology for lowering the dc power consumption, and the current-bleeding approach was adopted in mixer design for boosting its conversion gain, respectively. The proposed 24 GHz CMOS RF receiver achieves the overall conversion gain of 23.4 dB with noise figure of 5.4 dB, and the total power consumption is only 31.65 mW. Compared to the other papers published over the past few years, this paper exhibits a better potential in low-power design than other receivers applied in the same frequency band.