A continuous time ΔΣ ADC with clock timing calibration

A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.