Title :
A continuous time ΔΣ ADC with clock timing calibration
Author :
Tsai, Jen-Che ; Chen, Jhy-Rong ; Hsueh, Kang-Wei ; Chen, Mu-Jung
Author_Institution :
MediaTek Inc., Hsin-Chu
Abstract :
A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13 um CMOS process. The ADC achieves 75 dB dynamic range and 69 dB peak signal-to-noise ratio (SNR) at 1 MHz signal bandwidth and 64 MHz sampling rate while dissipating 2.2 mW from 1.2 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; sigma-delta modulation; 3-order multibit continuous-time delta-sigma ADC; CMOS process; clock timing calibration; excess loop delay compensation; frequency 1 MHz; frequency 64 MHz; power 2.2 mW; signal-to-noise ratio; size 0.13 mum; voltage 1.2 V; Adders; Bandwidth; CMOS process; Calibration; Circuit stability; Clocks; Delay; Dynamic range; PSNR; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708804
