Title :
A 57.1–59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique
Author :
Hung, Chao-Ching ; Lee, Chihun ; Cho, Lan-Chou ; Liu, Shen-Iuan
Author_Institution :
Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
In this paper, a 57.1-59 GHz fractional-N frequency synthesizer has been fabricated in 90 nm CMOS technology. A magnetic-coupled VCO achieves the high oscillation frequency and low phase noise. A harmonic-locked PD and a multi-modulus prescaler are adopted to double the sampling frequency of a second-order delta-sigma modulator. Theoretically, the quantization noise is improved by 12 dB with the same PLL bandwidth. It consumes 89 mW from a 1.2 V analog supply with output buffers and 16 mW from a 1.2 V digital supply. The chip occupies 0.86 times1.28 mm2 and the measured phase noise at 58.359375 GHz with the offset frequency of 2 MHz is -95.1 dBc/Hz.
Keywords :
CMOS integrated circuits; magnetic millimetre wave devices; millimetre wave devices; millimetre wave oscillators; modulators; phase locked loops; voltage-controlled oscillators; CMOS fractional-N frequency synthesizer; PLL bandwidth; frequency 57.1 GHz to 59 GHz; harmonic-locked PD; high-oscillation frequency; low-phase noise; magnetic-coupled VCO; multimodulus prescaler; power 16 mW; power 89 mW; quantization noise shifting technique; second-order delta-sigma modulator; voltage 1.2 V; Bandwidth; CMOS technology; Delta modulation; Frequency synthesizers; Magnetic noise; Phase locked loops; Phase noise; Quantization; Sampling methods; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708815