DocumentCode :
1834279
Title :
High-level synthesis of asynchronous systems by data-driven decomposition
Author :
Wong, Catherine G. ; Martin, Alain J.
Author_Institution :
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA, USA
fYear :
2003
fDate :
2-6 June 2003
Firstpage :
508
Lastpage :
513
Abstract :
We present a method for decomposing a high-level program description of a circuit into a system of concurrent modules that can each be implemented as asynchronous pre-charge half-buffer pipeline stages (the circuits used in the asynchronous R3000 MIPS microprocessor). We apply it to designing the instruction fetch of an asynchronous 8051 microcontroller, with promising results. We discuss new clustering algorithms that will improve the performance figures further.
Keywords :
asynchronous circuits; high level synthesis; microcontrollers; pipeline processing; asynchronous 8051 microcontroller; asynchronous VLSI; asynchronous system; clustering algorithm; concurrent module; data-driven decomposition; half-buffer pipeline stage; high-level synthesis; instruction fetch; Circuit synthesis; Clustering algorithms; Cogeneration; Computer science; Energy efficiency; High level synthesis; Microprocessors; Permission; Pipelines; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
Type :
conf
DOI :
10.1109/DAC.2003.1219060
Filename :
1219060
Link To Document :
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