Title :
A multi-band delay-locked loop with fast-locked and jitter-bounded features
Author :
Kuo, Chien-Hung ; Lin, Meng-Feng ; Chen, Chien-Hung
Author_Institution :
Dept. of Appl. Electron. Technol., Nat. Taiwan Normal Univ., Taipei
Abstract :
In this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 mum 1P6M CMOS process. The core area excluding PADs is 0.34times0.41 mm2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.
Keywords :
CMOS integrated circuits; UHF integrated circuits; delay lock loops; frequency multipliers; jitter; programmable circuits; CMOS process; DLL locking; fast-locked feature; frequency 200 MHz to 2 GHz; frequency multiplier; jitter-bounded feature; loop filter; multiband delay-locked loop; phase-frequency detector; power 31.5 mW; programmable charging voltage circuit; size 0.18 mum; tunable delay cell; voltage 1.8 V; Acceleration; CMOS process; Clocks; Delay; Filters; Jitter; Phase detection; Phase frequency detector; Tunable circuits and devices; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4244-2604-1
Electronic_ISBN :
978-1-4244-2605-8
DOI :
10.1109/ASSCC.2008.4708822
