Title :
Design and research of V-groove silicon avalanche electron emission array
Author_Institution :
Inst. of Power Device, Zhejiang Univ., Hangzhou, China
Abstract :
A V-groove structure is used to fabricate a silicon avalanche cathode (SAC). This novel structure for a SAC has a planar electron emission surface topology which reduces the channel current crowding effect and the current punch-through effect. The device structure and fabrication processing are described. A simple series resistance model and an effective electron emission area model are also discussed. A 12×12 cells arrayed device of this structure is designed and fabricated. Its I-V characteristics and emission characteristics are investigated, producing a better result than that of the traditional structure SAC
Keywords :
avalanche breakdown; electron field emission; elemental semiconductors; etching; ion implantation; semiconductor device models; semiconductor technology; silicon; vacuum microelectronics; I-V characteristics; Si; Si avalanche cathode; V-groove structure; avalanche electron emission array; channel current crowding effect reduction; current punch-through effect reduction; effective electron emission area model; emission characteristics; fabrication processing; planar electron emission surface topology; series resistance model; Conductivity; Electrodes; Electron emission; Epitaxial growth; Etching; Lithography; Predictive models; Silicon; Substrates; Surface resistance;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503323
