A cost-effective scan architecture for scan testing with nonscan test power and test application cost

A new scan architecture is proposed for full scan designed circuits. Scan flip-flops are grouped together if they do not have any common successors. This technique produces no new redundant faults. Scan flip-flops in the same group have the same values in all test vectors. All scan flip-flop groups form a scan forest, where each primary input drives the root of one scan tree. Test application time and test power based on the proposed scan forest architecture can be reduced drastically while pin overhead and delay overhead should be the same as that of conventional scan design. It is shown that test application cost and test power with the proposed scan forest architecture can be reduced to the level of nonscan design circuits.