An enhanced floating point coprocessor for embedded signal processing and graphics applications

There has been a marked interest in enhancing general purpose microprocessors to accommodate signal processing, primarily to improve audio and video compression routines and speech recognition algorithms. Presented here are several enhancements incorporated in the ARM VFPv1 floating point architecture which have demonstrated significant performance improvements on critical signal processing kernels. The first implementation of the VFPv1 architecture is the VFP10 floating point coprocessor macrocell. Discussed are the FMAC (floating point multiply-accumulate chained) instructions, a separate load/store pipeline for parallel processing of arithmetic and transfer operations, and SIMD capabilities for most arithmetic instructions designed to take advantage of a new recirculating register file structure.