Designing mega-ASICs in nanogate technologies

Author

Lackey, David E. ; Zuchowski, Paul S. ; Koehl, Juergen

Author_Institution

IBM Microelectron. Div., Essex Junction, VT, USA

fYear

2003

fDate

2-6 June 2003

Firstpage

770

Lastpage

775

Abstract

This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.

Keywords

application specific integrated circuits; integrated circuit design; integrated circuit economics; integrated logic circuits; nanotechnology; system-on-chip; time to market; ASIC design; application specific integrated circuit; circuit density; design productivity; design source; functional component integration; high density device geometry; logic gate; nanogate technology; power management; signal integrity; silicon technology; single chip solution; system product design; system-on-chip; time-to-market; Design methodology; Logic circuits; Logic design; Microelectronics; Power system reliability; Product design; Productivity; Rivers; Signal design; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219123

Filename

1219123