Exploring regular fabrics to optimize the performance-cost trade-off

Author

Pileggi, L. ; Schmit, H. ; Strojwas, A.J. ; Gopalakrishnan, P. ; Kheterpal, V. ; Koorapaty, A. ; Patel, C. ; Rovner, V. ; Tong, K.Y.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2003

fDate

2-6 June 2003

Firstpage

782

Lastpage

787

Abstract

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

Keywords

circuit optimisation; integrated circuit design; integrated circuit economics; performance evaluation; IC production; VPGA; design flexibility; design regularity; implementation flexibility; integrated circuit design; integrated circuit manufacturing; performance-cost trade-off; semiconductor technology; via patterned gate array; Application specific integrated circuits; CMOS technology; Cost function; Electronic design automation and methodology; Fabrics; Integrated circuit technology; Manufacturing; Moore´s Law; Productivity; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1219125

Filename

1219125