Title :
SAT-based unbounded symbolic model checking
Author :
Kang, Hyeong-Ju ; Park, In-Cheol
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
This paper describes a SAT-based unbounded symbolic model checking algorithm. BDDs have been widely used for symbolic model checking, but the approach suffers from memory overflow. The SAT procedure was exploited to overcome the problem, but it verified only the states reachable through a bounded number of transitions. The proposed algorithm deals with unbounded symbolic model checking. The proposed algorithm deals with unbounded symbolic model checking. The conjunctive normal form is used to represent sets of states and the transition relation, and a SAT procedure is modified to compute the existential quantification required in obtaining a pre-image. Some optimization techniques are exploited, and the depth first search method is used for efficient safety-property checking. Experimental results show the proposed algorithm can check more circuits than BDD-based symbolic model checking tools.
Keywords :
Boolean functions; binary decision diagrams; computability; formal verification; integrated circuit testing; logic design; BDD; SAT-based model checking; binary decision diagram; conjunctive normal form; depth first search method; formal verification; memory overflow; optimization technique; safety-property checking; satisfiability procedure; transition relation; unbounded symbolic model checking; Algorithm design and analysis; Boolean functions; Circuits; Data structures; Explosions; Formal verification; Iterative algorithms; Optimization methods; Permission; Search methods;
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
DOI :
10.1109/DAC.2003.1219136