DocumentCode :
1835872
Title :
VC-1 video decoder optimization on ARM Cortex-A8 with NEON
Author :
Pujara, Chirag ; Modi, Anurag ; Sandeep, G. ; Inamdar, Shilpa ; Kolavil, Deepa ; Tholath, Vidhu
Author_Institution :
Samsung India Software Oper. Pvt. Ltd., Bangalore, India
fYear :
2010
fDate :
29-31 Jan. 2010
Firstpage :
1
Lastpage :
5
Abstract :
Optimization of VC-1 Main profile decoder has been proposed using SIMD engine (NEON) of ARM Cortex-A8 processor. We have exploited data level parallelism to effectively use the SIMD capability of NEON. Ideas to make the algorithms SIMD friendly are also highlighted. With effective use of ARM Cortex-A8 architecture and NEON SIMD engine, the MCPS (Mega Cycles per second) requirement for decoding has reduced considerably as compared to our optimized C implementation. Results are provided for the overall performance gain in decoding and individual performance gain in various modules of VC-1 Main profile decoder.
Keywords :
microprocessor chips; optimisation; parallel architectures; video codecs; video coding; ARM Cortex-A8 architecture; ARM Cortex-A8 processor; MCPS; NEON SIMD engine; SIMD capability; VC-1 main profile decoder; VC-1 video decoder optimization; data level parallelism; mega cycles per second; Computer architecture; Data processing; Decoding; Displays; Encoding; Engines; Hardware; Parallel processing; Performance gain; Video codecs; Cortex-A8; NEON; Optimization; SIMD; VC-1; Video codec;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications (NCC), 2010 National Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4244-6383-1
Type :
conf
DOI :
10.1109/NCC.2010.5430200
Filename :
5430200
Link To Document :
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