An efficient greedy approach to PLA folding

Author

Bubna, Mayur ; Shenoy, Naresh ; Chattopadhyay, Santanu

Author_Institution

Dept. of Comput. Sc. & Eng., Indian Inst. of Technol., Kharagpur

fYear

2008

fDate

18-21 May 2008

Firstpage

1356

Lastpage

1359

Abstract

In this paper, a greedy approach for minimizing the area of a programmable logic array (PLA) using column folding of combinational component of finite state machines (FSMs) is presented. Also, the row reordering problem is addressed and a simple data structure is proposed to satisfy the constraints imposed by folding of columns. Genetic algorithm based formulation has been used for state encoding which gives minimally reduced two-level PLAs. Results obtained for several MCNC benchmark circuits show area improvement of 16.7% over NOVA[9], 53.1% over KISS[8] and 12.3% over STARF[7] on an average.

Keywords

encoding; finite state machines; genetic algorithms; greedy algorithms; matrix algebra; programmable logic arrays; benchmark circuits; finite state machines; genetic algorithm based formulation; greedy approach; programmable logic array; state encoding; Automata; Costs; Data structures; Decoding; Encoding; Field programmable gate arrays; Genetic algorithms; Logic arrays; Logic design; Programmable logic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4244-1683-7

Electronic_ISBN

978-1-4244-1684-4

Type

conf

DOI

10.1109/ISCAS.2008.4541678

Filename

4541678