Title :
Testability design with multiple scan chains
Author :
Ye, Bo ; Zheng, Zengyu ; Hu, Jun ; Li, Wei
Author_Institution :
Dept. of Electron. Eng., Fudan Univ., Shanghai, China
Abstract :
The methodology of constructing scan chains in a design with multiple scan chains is proposed in this paper. The multiple scan structure is also described. We discuss the method how to select scan path for different structured circuits and compare them with parallel scan structure. Experimental results show that test time is 1/K that of serial scan structure for a same circuit using this method while the hardware cost is less than that of parallel scan
Keywords :
design for testability; integrated circuit design; integrated circuit testing; integrated circuits; multiple scan chains; testability design; Circuit testing; Clocks; Feeds; Registers;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.503376
