DocumentCode
1836053
Title
Testability design with multiple scan chains
Author
Ye, Bo ; Zheng, Zengyu ; Hu, Jun ; Li, Wei
Author_Institution
Dept. of Electron. Eng., Fudan Univ., Shanghai, China
fYear
1995
fDate
24-28 Oct 1995
Firstpage
637
Lastpage
639
Abstract
The methodology of constructing scan chains in a design with multiple scan chains is proposed in this paper. The multiple scan structure is also described. We discuss the method how to select scan path for different structured circuits and compare them with parallel scan structure. Experimental results show that test time is 1/K that of serial scan structure for a same circuit using this method while the hardware cost is less than that of parallel scan
Keywords
design for testability; integrated circuit design; integrated circuit testing; integrated circuits; multiple scan chains; testability design; Circuit testing; Clocks; Feeds; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-3062-5
Type
conf
DOI
10.1109/ICSICT.1995.503376
Filename
503376
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