Author :
Steffen, Michael ; Allada, Veerendra ; Jones, Phillip ; Zambreno, Joseph
Author_Institution :
Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
Abstract :
The 2010 MEMOCODE Hardware Software Co-design challenge is to implement a Deep Packet Inspection architecture, called the CANSCID - Combined Architecture for Stream Categorization and Intrusion Detection. In this short paper, we present the design details of our submission, that utilizes a Graphical Processing Unit (GPU) to accelerate the parallel regular expression matching. The target line rate of 500 Mbps is met on all of the 25 mandatory and 10 optional patterns. The design is developed using the NVIDIA CUDA framework and tested on the Tesla GPU.
Keywords :
computer graphic equipment; coprocessors; deterministic automata; finite automata; hardware-software codesign; parallel architectures; security of data; 2010 MEMOCODE hardware software codesign challenge; CANSCID-CUDA; NVIDIA CUDA; Tesla GPU; combined architecture for stream categorization and intrusion detection; deep packet inspection architecture; deterministic finite automata; graphical processing unit; parallel regular expression matching; Computational modeling; Data models; Data structures; Graphics processing unit; Instruction sets; Kernel; Pattern matching; CUDA; Deterministic Finite Automata (DFA); General Purpose Computing on Graphical Processing Units (GPGPU); JLex; Python;
Conference_Titel :
Formal Methods and Models for Codesign (MEMOCODE), 2010 8th IEEE/ACM International Conference on
Conference_Location :
Grenoble
Print_ISBN :
978-1-4244-7885-9
Electronic_ISBN :
978-1-4244-7886-6
DOI :
10.1109/MEMCOD.2010.5558644
