Power consideration in mapping LUT based FPGA circuits

In this paper is presented a new approach for decreasing the functional power consumption in LUT based FPGA implemented circuits. The attempt is based on reducing logic activity among LUTs. In order to achieve this target it was used the simulation-based approach that estimates, using a Monte Carlo experiment, the dynamic switching activity of each line in the circuit. Traversing circuits from primary inputs lines to the primary output lines, step by step stationary probability and transition distribution are computed at the output of each gate. Preserving the best depth of the circuits the mapping stage is done searching to hide high transition lines inside LUTs.