Design of an economical 3.8 GHz oscillator which gives low phase noise of −120 dBc/Hz at off-set frequency of 100 Hz–100 kHz

This paper presents a method to design an economical low phase noise 3.8 GHz oscillator using NPN BJT transistor and the FR4 board. The proposed cost-effective oscillator design exhibited a low phase noise of -120 dBc/Hz at off-set frequency of 100 Hz-100 kHz. The oscillating frequency is 3.7848 GHz with an output power of -2.83 dBm. The phase noise achieved is much better than oscillator fabricated using CMOS technology used by most researchers. It is hope that the lower phase noise oscillator designed using BJT will improves performance of Doppler Radar and OFDM communications systems. This paper uses the low cost FR4 substrate in designing the 3.8 GHz oscillator by taking into consideration changes in the dielectric constant of the FR4 with frequency.