An FPGA implementation of an all digital phase locked loop for control applications

This paper proposes a way of implementing a phase locked loop (PLL) controller. The focus is on the FPGA implementation of the digital PLL. The control is based on a closed loop, the sensing element being an optical tachometer. The output of the tachometer is compared to a reference signal, and a pulse width modulated (PWM) signal is derived, based on the phase and frequency error, to adjust the system output. The phase and frequency error is determined by a digital phase/frequency detector and is delivered as a PWM signal. This error signal is measured by the digital circuitry and passed to the loop filter of the PLL, which acts as the regulator. The main result is the phase error measurement circuitry. It has a numeric output, which allows the design of a digital loop filter. The design of the PLL can be done only with digital logic. The whole digital controller can be easily implemented in an FPGA.