Algorithm and circuit co-design for a low-power sequential decoder

The design of a sequential decoder for a convolutional code in a mobile radio environment with the objective of minimizing the average decoding effort and hence the energy consumption is presented. An efficient normalization scheme and a corresponding fast, low-energy architecture is proposed. We present the chip layout and Powermill simulation results in 0.5 /spl mu/m HP14B CMOS technology. For sufficiently high SNR, the proposed design performs close to that of the optimal Viterbi decoder. The average energy consumption per decoded bit for the proposed architecture is compared against a baseline Viterbi decoder design for a simple AWGN channel. The AWGN performance characteristics are translated into average energy consumption per decoded bit for a nominal cellular system mobile unit accounting for fading and mobility. For realistic operational scenarios, the proposed architecture consumes only 7.2% as much energy as the Viterbi baseline.