High-performance low-power AND and Sense-Amp address decoders with selective precharging

This paper presents and evaluates two novel address decoding schemes that use selective precharging, the sense-amp and the AND decoders, in comparison to the conventional NOR decoder. Simulations for all three designs are performed using 65 nm CMOS technology and the delays of all three decoders are set to 120 ps for a common base comparison. The most selective AND decoder performs best and dissipates between 0.17% and 43.17% (29.29% on average) and the selective Sense-Amp decoder dissipates between 28.81% and 48.33% (39.96% on average) of the energy dissipated by the nonselective conventional decoder.