Title :
An alias-locked loop frequency synthesis architecture
Author :
Van den Berg, Leendert ; Elliott, Duncan G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB
Abstract :
This paper presents a phase-locked loop (PLL) using an aliasing divider, referred to as an alias-locked loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path. To examine the lock-in behaviour of the alias-locked loop, a nonlinear model is developed and used to simulate the architecture in the locked state. Simulation results demonstrate the existence of stable modes of operation with bounded orbits. A version of the ALL is designed in 90-nm CMOS technology and simulated.
Keywords :
CMOS integrated circuits; frequency synthesizers; network synthesis; phase locked loops; ALL architecture; CMOS technology; alias-locked loop frequency synthesis architecture; aliasing divider; bounded orbits; feedback path; high-speed frequency synthesis circuits; lock-in behaviour; locked state; nonlinear model; phase-locked loop; size 90 nm; CMOS technology; Circuit simulation; Circuit synthesis; Feedback circuits; Frequency conversion; Frequency locked loops; Frequency synthesizers; Orbits; Phase locked loops; Semiconductor device modeling;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541723
