An alias-locked loop frequency synthesis architecture

This paper presents a phase-locked loop (PLL) using an aliasing divider, referred to as an alias-locked loop (ALL). The ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider in the feedback path. To examine the lock-in behaviour of the alias-locked loop, a nonlinear model is developed and used to simulate the architecture in the locked state. Simulation results demonstrate the existence of stable modes of operation with bounded orbits. A version of the ALL is designed in 90-nm CMOS technology and simulated.