Title :
Characterization of the HDP-CVD oxide as interlayer dielectric material for sub-quarter micron CMOS
Author :
Kim, Ju Wan ; Lee, Ju Bum ; Hong, Jin Gi ; Hwang, Byung Keun ; Kim, Sung Tae ; Han, Min Soeg
Author_Institution :
Samsung Electron. Co. Ltd., Youngin-City, South Korea
Abstract :
The characteristics and process optimization of high density plasma (HDP) CVD oxide as a wordline to bitline interlayer dielectric (ILD) material in sub-quarter micron CMOS DRAM were investigated. To enhance the gap-filling capability, multi-step deposition of HDP CVD oxide was developed. A self-aligned contact (SAC) scheme could be used with HDP CVD oxide ILD with wide process margin and low thermal budget as compared to conventional methods such as O3-TEOS undoped silicate glass (USG) and borophosphosilicate glass (BPSG) reflow. Better or comparable performance was obtained with HDP CVD oxide compared to BPSG-reflow due to the low thermal budget
Keywords :
CMOS memory circuits; DRAM chips; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; optimisation; plasma CVD; silicon compounds; B2O3-P2O5-SiO2; BPSG; BPSG-reflow; CMOS DRAM; HDP CVD oxide; HDP CVD oxide ILD; HDP-CVD oxide interlayer dielectric material; O3; O3-TEOS undoped silicate glass; SiO2-Si; borophosphosilicate glass reflow; gap-filling capability; high density plasma CVD oxide; multi-step deposition; process margin; process optimization; self-aligned contact scheme; thermal budget; wordline to bitline interlayer dielectric; Chemical vapor deposition; Dielectric materials; Dry etching; Glass; Optical microscopy; Plasma applications; Random access memory; Scanning electron microscopy; Sputtering; Wet etching;
Conference_Titel :
Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-4285-2
DOI :
10.1109/IITC.1998.704921
