FPGA implementation of 2D wavelet transform

The implementation of the 2D wavelet transform for real-time processing in FPGA is discussed. This implementation is intended for real-time image processing and compression. The proposed approach uses a cascade combination of two 1D wavelet transforms along with a set of in-chip memory buffers, between the two stages. The required memory buffer for holding intermediate results is optimized by proper pipelining of the data transfer between the two stages. Implementation of this architecture is suitable for new Xilinx Virtex FPGAs that offer enough memory on the chip for storage of intermediate results. In this case, there is no need for external RAM modules and the complete 2D transform can be implemented on a single chip. One major advantage of this methodology is the flexibility that is offered to the user in terms of freedom for selection of the wavelet filter and tree-structure.