Deterministic High Density Packet-Buffer System for Low Cost Network Systems

Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density requires complex memory management. As a result it, it has hardly supported large numbers of queue, which is an effective solution in QoS. This paper proposes an intelligent memory management unit (MMU) in the bases of hybrid architecture, wherever 16k multi queues are integrated. The performance examined by the system board is zero-packet loss under the seamless traffic with 60-1.5k Byte packet-length. (deterministic manner) Noticeable feature in this paper´s architecture is eliminating any premium memories but uses only low-cost commodity SRAMs and DRAMs. The intelligent MMU involves head buffer architecture, which is suitable to support a large numbers of FIFO queues. The experimental board based on this architecture is embedded into a Router system to evaluate the performance. Using 16k queues at 20Gbps, zero-packet loss is examined with 64-Byte to 1, 500-Byte packet-length.