Integration challenges for high-performance carbon nanotube logic

As the scaling of silicon-based devices becomes more challenging, alternative channel materials are being actively explored. One approach is to replace the silicon channel with nanoparticles - for example, carbon nanotubes - that offer higher performance and better scaling potential. However, the incorporation of nanoparticles requires the development of new “bottom up” fabrication techniques to grow or place particles at precise locations on a substrate. The inherent randomness of these assembly processes has an obvious impact on device yield, which must be taken into account in optimizing the layout of a device. Here we describe a simple statistical analysis of device yield that can give insight into the self-assembly process, and is particularly useful for characterizing nanoparticle self-assembly from solution.